The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for analyzing and debugging circuitry within an integrated circuit.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages.
A by-product of such high-density and high functionality is an increased demand for products employing these microprocessors and devices for use in numerous applications. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased. Such devices often require manufacturing processes that are highly complex and expensive.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that an individual die is functional, it is also important to ensure that batches of dice perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Many semiconductor device characteristics are temperature-related. For example, defective circuitry can recover or fail at high temperatures. Circuit sites exhibiting temperature sensitive defects, such as charge trapping and ionic contamination, can recover when heated. Other sites exhibiting temperature sensitive defects, such as resistive interconnects, can fail when heated. These temperature-related characteristics can cause operational instability, and can ultimately result in circuit failure.
In many applications, the area available for accessing semiconductor device circuitry also limits the ability to test the circuitry, as well as limits the quality of data that can be collected when analyzing temperature-related characteristics. This access area becomes increasing smaller as semiconductor devices are scaled down in size with increasing amounts of circuitry therein, and as device feature size approaches the sub-micron regime. For example, active circuit regions (e.g., source/drain regions) are being formed having feature sizes that are less than one micron in width. However, previously-available approaches to circuit access (e.g., for stimulating circuitry) have been limited in resolution, which typically has been limited to one micron. In addition, accessing circuitry can sometimes alter or destroy the circuitry being tested. These and other considerations have presented challenges to the design, manufacture and analysis of semiconductor devices.
Addressing the above and other concerns, the present invention is directed to the analysis of an integrated circuit die involving heat exchange. The analysis can be effected via the back side or the front side of the die. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device is probed using sub-micron resolution to apply and/or withdraw heat from a selected circuit in the device. A response (or lack thereof) of device to the heating and/or cooling is then detected and used to analyze the device. With this approach, a surface area of circuitry that is less than one micron2 can be individually heated and/or cooled and a response of the device thereto can be used for the analysis. Defects and other circuit conditions can then be analyzed, addressing challenges to the manufacture and analysis of semiconductor devices, such as those discussed hereinabove.
According to another example embodiment of the present invention, a system is arranged for probing a semiconductor device using sub-micron resolution. The system includes a probe configured and arranged to exchange heat with the die and a navigational arrangement configured and arranged to direct the probe within one micron of a selected portion of the die. With this approach, the heat exchange is predominantly confined to within about a one micron radius on a lateral plane of the semiconductor device (e.g., with the lateral plane being perpendicular to the direction of the heat exchange).
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.